This invention relates, in general, to semiconductor products, and more particularly, to making semiconductor devices.
At the present time, separation and isolation of n+buried layers or n+ buried collectors in a substrate is achieved by placing a p buried isolation layer between the n+ buried layers or n+ buried collectors. It should be understood that hereinafter references made to n+buried collector will include n+ buried layers. Conventionally, the p buried layer is made by a multi-step process, using photolithography and ion implantation. Typically, the photolithography is achieved with well-known conventional methods which expose or open areas between the buried layers, while other areas are covered or protected by a photoresist layer. The exposed or open areas are then implanted with a suitable p dopant, thereby producing a p region between the n+buried collectors. Upon subsequent processing the p region is diffused and activated to form a p buried layer between the n+ buried collectors that is more heavily doped than the substrate. However, as semiconductor devices continue to shrink, while at the same time increasing in complexity, isolation or separation problems between n+ buried collectors become more apparent and affect the semiconductor devices that are made with the conventional methods. The conventional methods of isolation or separation of n+ buried collectors result in several problems, such as punchthrough problems between the two n+ buried collectors, capacitance problems between the n+buried collectors and the p buried layers, and additional processing to make the p buried layer. Ultimately, these problems result in poor performance of the semiconductor device as well as yield failures
It can be readily seen that conventional methods of placing isolation or separation areas between the buried layers or buried collectors is not sufficient for semiconductor devices that require higher performance and have reduced size. Additionally, because of the decreasing size of the semiconductor devices and the increasing complexity of the semiconductor devices, problems with isolation and separation of buried layers or buried collectors will increase. Therefore, a method for making a bipolar semiconductor device that allows for reduction of parasitic capacitance while avoiding punchthrough, and reduction of the number of processing steps for making the p buried isolation layer would be highly desirable.